Control-flow checking using watchdog assists and extended-precision checksums

troller), it has the advantage of maintaining sequential consistency, thus allowing parallel programs to work as expected. VII. SUMMARY AND CONCLUSIONS The delays due to error checking being performed in series with intermodule communication are one of the primary causes of performance degradation associated with implementing concurrent error detection and correction in VLSI systems. This performance penalty may be caused by dedicated checkers in the communication paths between each module and the rest of the system or the need to wait for the hardware to perform redundant operations that verify the validity of the " recent " results. Checks that are area efficient are usually serial and slow, and faster checks are often based on checkers which take up large area, thus slowing down surrounding circuits. Checking delays are compounded when data are transferred between several modules, and checked at several places. This fundamental problem in achieving fault tolerance in high-performance VLSI systems can be overcome by performing checks on the data in parallel with intermodule communication. Data to be checked can be latched, and error checking can take place in one or more subsequent cycles (as a pipeline). As a consequence, error signals can arrive one or more cycles after error-damaged data are received for processing. In this paper, we have described a mechanism , called micro rollback, which allows checking to proceed in parallel with communication by supporting fast rollback of a few cycles when a delayed error signal arrives. Micro rollback is a powerful technique that facilitates the implementation of high-performance VLSI systems which are also highly fault tolerant. It allows a variety of concurrent error detection and correction techniques to be used with minimal performance penalty. With micro rollback, it is feasible to operate systems in hostile environments, where there is a high rate of transient faults, due to the ability of individual modules to initiate rollback and retry which can complete in a few cycles without resorting to expensive system-wide rollbacks. We have presented a systematic way to design VLSI computer modules that can roll back and restore the state which existed when the error occurred. Specifically, the implementation of micro rollback in simple synchronous systems involves replication of small isolated registers and the use of full delayed-write buffers (DWB's) for storing recent state changes to large register files. When applied to a VLSI RISC processor, the micro rollback technique is characterized by extremely low …